Latest posts by Larry Moberg (see all)
- 2015-08-21 Librem 13: Weekly BIOS Progress Update - August 24, 2015
- 2015-08-14: Librem 13: Weekly BIOS Progress Update - August 14, 2015
- Roadmap To A Completely Free BIOS - August 5, 2015
This post covers the Librem 13 engineering considerations around writing to the SPI flash chip, and how that affects coreboot development. This builds on last week’s notes on the low level I/O for debugging coreboot builds. As always, email questions or comments to: email@example.com.
The BIOS flash on the Librem 13 is an 8 MiB chip in a SOP-8 package. The EC firmware is located on a separate 64 KiB chip. This link can be used to locate the chips on your mainboard: the BIOS flash is halfway down, near the CPU heatpipe. The EC flash is at the bottom just below the DDR3L module.
Even without any patches specifically for the Librem 13, flashrom can flawlessly read its BIOS flash because it supports the PCH. Unless you write outside the BIOS region, you will not encounter any problems using flashrom to update your BIOS.
Please don’t update the Intel Firmware Descriptor or ME region just yet–all the IFD bits are marked read/write and flashrom is happy to execute a write to that region. The issue arises because the ME writes asynchronously to the ME region. A collision of flashrom and ME writes will corrupt the ME region and may brick the laptop. Purism intends to provide an unlocked ME that respects your freedom, so look for an update on the Purism blog.
In-System Programming The BIOS Flash
The BIOS can be written and verified using a SOP-8 clip after closing the two sides of jumper J1 to assert the PCH RSMRST# pin. Warning: reflashing the BIOS risks bricking the laptop until in-system programming and/or soldering a new BIOS chip restores the BIOS to a good state.
The KB3930 datasheet, section 3.1 “Hardware Trap,” gives the method for programming the EC flash:
- Disconnect the battery and the A/C power so that the EC is fully powered down.
- Pull GPIO23/TP_ISP (pin 42) to GND. Note the internal 40K-ohm pull-up resistor.
- Connect the A/C power supply to the board. The EC is now powered up.
- TP_ISP sets CS#, SPI_CLK, MISO, and MOSI lines “High-Z”.
- Connect a SOP-8 clip and flash programmer and flash the EC firmware.
It should be noted fine-pitch soldering is required to connect to pin 42 on the EC. The KB3930 also supports firmware updates via software. We will be developing a clean room Free Software EC firmware that has all the same functionality as the existing EC firmware.
This post covers the steps for coreboot development and recovery. Fortunately, the EC firmware is not shared with the BIOS or ME blob, which makes flashrom’s job easier.
BIOS development is hard. One of the major challenges facing BIOS developers is a lack of accurate, comprehensive documentation for all the hardware coreboot interacts with. The “elephant in the room,” for an Intel-based laptop, is the Management Engine.
[Ed. Note: this was reposted from blogs.coreboot.org with permission.]